A vertical IGFET, as defined herein, refers to a transistor wherein current flow is regulated along a direction which is perpendicular to the major surfaces of the substrate on which the transistor is disposed. The source, body and drain regions are in an overlying relationship to one another, and an insulated gate electrode is contiguous with at least a portion of the body region. When the insulated gate electrode is appropriately electrically biased, an inversion channel is formed between the source and drain regions in that portion of the body region adjacent thereto. The fundamental structure for such a vertical IGFET device is disclosed in copending U.S. patent application Ser. No. 489,307, SELF-ALIGNED VERTICAL IGFET AND METHOD FOR FABRICATING SAME, L. L. Jastrzebski et al., filed Apr. 28, 1983 and now U.S. Pat. No. 4530149.
The fundamental structure includes a substrate having a monocrystalline portion at a major surface thereof and an insulated gate electrode disposed on the substrate surface. The insulated gate electrode, which comprises a conductive gate electrode which is substantially surrounded by gate insulation, includes an aperture to an area of the monocrystalline portion. A monocrystalline silicon region extends from the substrate within the aperture to a height substantially equal to that of the insulated gate electrode. That part of the monocrystalline silicon region within the aperture and in opposition to the conductive gate electrode is doped so as to form the body region of the FET. Thus, the thickness of the conductive gate electrode determines gate length. Parts of the monocrystalline silicon region underlying and overlying the body region are oppositely doped so as to form source and drain regions.
Such vertical IGFETs can be fabricated utilizing the epitaxial lateral overgrowth (ELO) fabrication technique disclosed in copending U.S. patent application Ser. No. 338,958, METHOD FOR GROWING MONOCRYSTALLINE SILICON ON A MASK LAYER, J. F. Corboy et al., filed Jan. 12, 1982 and now abandoned. Basically, the ELO process involves a repetitious, two phase, deposition/etch cycle whereby monocrystalline silicon is grown from a monocrystalline surface which is exposed within the aperture of an overlying mask.
The structure of a CMOS device couples an N-channel IGFET with a P-channel IGFET by a common gate electrode. The gate electrode in a conventional CMOS device is insulated by an oxide layer. Although the basic principles of a CMOS device apply to the structure of the present invention, it should be recognized that the present invention does not limit the gate insulation to be oxide.